Accurate target detection system for compensating detector background levels and changes in signal environments

ABSTRACT

An accurate target detection system. The system includes a sensor ( 22 ) that receives electromagnetic signals and provides electrical signals in response thereto. A non-uniformity correction circuit ( 28, 38, 52 ) corrects non-uniformities in the sensor ( 22 ) based on the electrical signals and provides calibrated electrical signals in response thereto. A third circuit ( 30, 32, 34, 38, 42, 44, 52 ) determines if a target signal is present within the calibrated electrical signals and provides a target detection signal in response thereto. A fourth circuit ( 38, 40, 48 ) selectively activates or deactivates the non-uniformity correction circuit ( 28, 38, 52 ) based on the target detection signal. In a specific embodiment, the sensor ( 22 ) is an array of electromagnetic energy detectors ( 22 ), each detector providing an electrical detector output signal. The non-uniformity correction circuit ( 28, 38 , and  52 ) includes circuit for compensating for gain, background, and noise non-uniformities ( 28, 38 , and  52 ) in the electromagnetic energy detectors. The non-uniformity correction circuit ( 28, 38 , and  52 ) includes a detector gain term memory ( 28 ) for storing detector gain compensation values. The detector gain compensation values are normalized by noise estimates unique to each of the detectors. The third circuit ( 30, 32, 34, 38, 42, 44 , and  52 ) includes a signal enhancement circuit for reducing noise ( 34, 42 ) in the calibrated electrical signals. The third circuit ( 30, 32, 34, 38, 42, 44 , and  52 ) includes a noise estimation circuit ( 32, 38 ) that estimates noise in each of the detector output signals and provides noise estimates in response thereto. The noise estimation circuit ( 32, 38 ) further includes a noise estimator circuit ( 38 ) and a recursive background estimator ( 32 ).

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to target detection systems. Specifically, thepresent invention relates to systems employing electro-optical sensorsto detect targets using constant false alarm rate detection processes.

2. Description of the Related Art

Target detection systems are used in a variety of demanding applicationsincluding radar air traffic control systems, missile target trackingsystems, and electro-optical target detection systems employed onaircraft and ground-based military vehicles. Such applications oftenrequire accurate target detection systems that produce minimal falsedetections.

A target detection system typically includes an electromagnetic energysensor that receives electromagnetic signals such as optical signals andoutputs electronic signals in response thereto. A processing circuitanalyzes the electronic output signals to determine if a target ispresent in the field of view of the sensor.

The sensor is often a focal plane array of electromagnetic energydetectors such as charge-coupled devices (CCDs). Detectors in the arraymay have different performance characteristics that may change with achanging signal environment. Often, the detectors are initiallycalibrated by aiming the sensor at a dark, uniform region of space.Electrical offset values or gain coefficients are applied to the outputsof the detectors to equalize the outputs and thereby compensate fordetector signal non-uniformities.

In a typical constant false alarm rate (CFAR) target detection system,the processing circuit includes a detector non-uniformity correctioncircuit for performing the calibration, a background estimation circuit,and a threshold circuit. The background estimation circuit determines aninitial background value that is subtracted from the outputs of thedetectors to enhance signal-to-noise ratio. The threshold circuitestablishes a detection voltage threshold range for the detectors in thearray. Typically, a single threshold range is established for alldetectors in the array.

An ‘alarm’ occurs when the magnitude of a detector output signal iswithin the threshold range. By controlling the threshold range, thetarget detection system can control the probability of making a falsedetection. However, decreasing the probability of false detection mayincrease the likelihood that a target will go undetected.

Use of a single threshold range for all detectors in the array isinefficient, as the performance capabilities of individual detectors areoften not maximized. For example, low performance detectors may raisethe desired lower threshold of the threshold range. Due to the higherthreshold, the capability of any high performance pixels to detecttargets in noisy environments is not utilized.

Detector background estimation is often performed when the targetdetection system is initially activated and is disabled thereafter. Inexisting systems, if the background estimation circuit remains enabled,target information may corrupt the background estimates. The corruptedvalues may greatly reduce the target detection capability of the system.Accordingly, many existing target detection systems fail to account forvariations in background that often occur during system operation. As aresult, the ability of such target detection systems to accuratelydetect targets is compromised.

Hence, a need exists in the art for an accurate target detection systemthat accounts for varying detector background levels and changing signalenvironments during system operation.

SUMMARY OF THE INVENTION

The need in the art is addressed by the accurate target detection systemof the present invention. In the illustrative embodiment, the inventivesystem is adapted for use with electro-optical systems and includes afirst circuit for receiving electromagnetic signals and providingelectrical signals in response thereto. A second circuit correctsbackground non-uniformities and/or noise in the first circuit based onthe electrical signals and provides calibrated electrical signals inresponse thereto. A third circuit determines if a target signal ispresent within the calibrated electrical signals and provides a targetdetection signal in response thereto. A fourth circuit selectivelyactivates or deactivates the second circuit based on the targetdetection signal.

In a specific embodiment, the first circuit is an array ofelectromagnetic energy detectors, each detector providing an electricaldetector output signal. The second circuit includes a non-uniformitycorrection circuit for compensating for gain non-uniformities and noisenon-uniformities in the electromagnetic energy detectors. The secondcircuit includes a detector gain term memory for storing detector gaincompensation values. The detector gain compensation values arenormalized by noise estimates unique to each of the detectors. The thirdcircuit includes a signal enhancement circuit for increasing thesignal-to-noise ratio of the calibrated electrical signals. The thirdcircuit includes a noise estimation circuit for estimating noise in eachof the detector output signals and providing noise estimates in responsethereto. The noise estimation circuit further includes a noise estimatorand a recursive background estimator. The third circuit further includesa subtractor for subtracting background contained in the noise estimatesfrom the calibrated electrical signals and providing backgroundsubtracted signals in response thereto. The signal enhancement circuitincludes a frame integrator circuit for summing frames of image data andproviding summed frames in response thereto. Each frame of image datacontains data corresponding to the background subtracted signals. Thesignal enhancement circuit further includes a filter bank that enhancesthe signal-to-noise ratio of the summed frames and provides a filteredsignal in response thereto. The third circuit includes a first thresholdcircuit for comparing the filtered signal to a first threshold and asecond threshold and providing a threshold exceedance signal if thefiltered signal is between the first threshold and the second threshold.

In the illustrative embodiment, the third circuit further includes adigital signal processor running a controller that facilitates thedetermination of the first threshold by providing a threshold multipliervalue. The first threshold is a function of the threshold multiplier andnoise variables for the background subtracted signals. The noisevariables include a mean noise offset, noise variance estimates from thebackground subtracted signals, and a noise statistic for accounting formoments greater than two in noise statistics of the backgroundsubtracted signals. The fourth circuit includes a second thresholdcircuit for comparing the background subtracted signals to a targetdetection threshold and providing the target detection signal inresponse thereto when the background subtracted signals exceed thetarget detection threshold. The target detection signal acts as aninhibit signal and is input to background and noise estimation circuitsto disable the estimation circuits when the target signal is possiblypresent with in the background subtracted signals. The first thresholdis a function of the noise variance estimates and a second thresholdmultiplier.

The novel design of the present invention is facilitated by use of thesecond threshold circuit to selectively inhibit background updates andnoise estimation calculations for the outputs of detectors of the sensorthat possibly represent target data. As a result, background estimationfunctions and noise estimation functions may continue to run duringoperation of the target detection system of the present invention. Thisallows the target detection system of the present invention to track anychanges in signal environment and detector noise performance duringsystem operation. This greatly increases the ability of the targetdetection system of the present invention to detect targets in noisyenvironments. Furthermore, use of threshold levels unique to eachdetector in the second threshold circuit and the first threshold circuitallows the present invention to optimize the target detectioncapabilities of each detector in the sensor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a target detection system constructed inaccordance with the teachings of the present invention.

FIG. 2 is a diagram of the recursive background estimator of the targetdetection system of FIG. 1.

FIG. 3 is a diagram of the noise estimator of the target detectionsystem of FIG. 1.

FIG. 4 is a diagram of the frame integrator of the target detectionsystem of FIG. 1.

FIG. 5 is a diagram of the matched filter bank of the target detectionsystem of FIG. 1.

FIG. 6 is a diagram of a diagram of a finite impulse response (FIR)filter of the filter bank of FIG. 5.

FIG. 7 is a diagram showing key functional blocks of a fuzzy thresholdcontroller implemented in the digital signal processor of the targetdetection system of FIG. 1.

FIG. 8 is a graph of the input feature of the fuzzy threshold controllerof FIG. 7.

FIG. 9 is a graph of the output feature of the fuzzy thresholdcontroller of FIG. 7.

DESCRIPTION OF THE INVENTION

While the present invention is described herein with reference toillustrative embodiments for particular applications, it should beunderstood that the invention is not limited thereto. Those havingordinary skill in the art and access to the teachings provided hereinwill recognize additional modifications, applications, and embodimentswithin the scope thereof and additional fields in which the presentinvention would be of significant utility.

FIG. 1 is a diagram of a target detection system 20 constructed inaccordance with the teachings of the present invention. The targetdetection system 20 includes a sensor 22, the output of which isconnected to a analog-to-digital converter (ADC) 24. An output of theADC 24 is connected to a first input of a first multiplier 26. A secondinput of the first multiplier 26 is connected to an output of anormalized detector gain term memory 28. An output of the firstmultiplier 26 is connected to a positive terminal of a subtractor 30. Anegative terminal of the subtractor 30 is connected to an output of arecursive background estimator 32. An output of the subtractor 30 isconnected, in parallel, to an input of a frame integrator 34, a framestore 36, a noise estimator 38, and a uni-level threshold circuit 40. Anoutput of the uni-level threshold circuit 40 is connected, in parallel,to an input of the recursive background estimator 32 and an input of thenoise estimator 38. An output of the frame integrator 34 is connected toa filter bank 42. An output of the filter bank 42 is connected to aninput of a bi-level threshold circuit 44, an output of which isconnected to an address generator 46. An output of the noise estimator38 is connected, in parallel, to an input of a second multiplier 48 anda first input of a third multiplier 50. Another input of the secondmultiplier 48 is connected to a digital signal processor (DSP) 52. Anoutput of the second multiplier 48 is input to the uni-level thresholdcircuit 40. A second input of the third multiplier 50 is connected to anoutput of a TNR random access memory (TNR RAM) 54. A third input of thethird multiplier is connected to the DSP 52. An input of the TNR RAM 54is also connected to the DSP 52. An output of the third multiplier 50 isconnected to an input of an adder 56. Another input of the first adder56 is connected to the DSP 52. An output of the adder 56 is input to thebi-level threshold circuit 44. The bi-level threshold circuit 44 alsoreceives additional input from the DSP 52. The DSP 52 is also connectedto the normalized detector gain term memory 28, the recursive backgroundestimator 32, the noise estimator 38 and the filter bank 42 via a busconnection 60. An inertial reference unit 58 provides input to the DSP52.

In the present specific embodiment, the sensor 22 is a focal plane arrayof electro-optical detectors such as charge-coupled devices. Eachdetector provides an output signal corresponding to a pixel in a frameof image data. Each frame of image data represents output signals fromeach of the detectors during a predetermined time interval. Thepredetermined time interval is based upon a system frame rate. Thesystem frame rate may vary in accordance with requirements for aparticular application and is easily implemented via clocks, timers, andsynchronizing circuits by those ordinarily skilled in the art.

In operation, the sensor 22 receives electromagnetic energy within afield of view of the sensor 22 and converts the electromagnetic energyinto an analog electrical signal that is transferred to the ADC 24. TheADC 24 converts the analog electrical signal into a digital signalS_(ij). The digital signal S_(ij) represents the digitized outputs ofdetectors in the sensor 22 when the sensor 22 is an array of detectorshaving i rows and j columns. The digital signal S_(ij) is input to thefirst multiplier 26, which is a digital multiplier.

The normalized detector gain term memory 28 has i times j memorylocations, one location for each detector in the sensor 22. Each memorylocation stores correction terms G_(ij)/σ_(ij) for each ij detector inthe sensor 22. The correction terms G_(ij)/σ_(ij) are a ratio of gainnon-uniformity correction terms G_(ij) and noise terms σ_(ij). TheG_(ij) terms are initially determined in a laboratory environment andare specific to each detector in the sensor 22. The noise terms σ_(ij)are updated during system operation via the DSP 52. The DSP 52 runssoftware that reads noise variance terms σ_(ij) ² from the noiseestimator 38, computes the square root of the noise variance termsσ_(ij) ², and provides the resulting noise estimates to the normalizeddetector gain term memory 28 via the buss connection 60. The noisevariance terms σ_(ij) ² are continually updated during operation of thetarget detection system 20 when not inhibited from doing so by aninhibit signal from the uni-level threshold circuit 40.

Those skilled in the art will appreciate that updating of the noiseterms σ_(ij) may be implemented in hardware and may be computed withoutfirst computing the noise variance terms σ_(ij) ² without departing fromthe scope of the present invention.

The correction terms G_(ij)/σ_(ij) from the normalized detector gainterm memory 28 are multiplied with digital signal S_(ij) via the firstmultiplier 26. The first multiplier 26 outputs a calibrated signalcomprising S_(ij)(G_(ij)/σ_(ij)) terms to the positive terminal of thesubtractor 30. Initially, the negative terminal of the subtractor 30 iszero, and the calibrated signal S_(ij)(G_(ij)/σ_(ij)) initializes theframe store 36, the uni-level threshold circuit 40, the noise estimator38, and the recursive background estimator 32.

Those skilled in the art will appreciate that the recursive backgroundestimator 32, the noise estimator 38, the frame integrator 34, and theframe store 36 may be pre-initialized via software running on the DSP 52without departing from the scope of the present invention.

Once initialized, the recursive background estimator 32 providesbackground estimates B_(ij) to the negative terminal of the subtractor30. Initially, the background estimates B_(ij) are based on thebackground in the calibrated signal S_(ij)(G_(ij)/σ_(ij)) and thereafterare based on an average of past frames of image data representing anaccumulation of S_(ij)(G_(ij)/σ_(ij))−B_(ij) terms from the output ofthe subtractor 30. The number of frames to be averaged by the recursivebackground estimator 32 is controllable via software running on the DSP52. The software is easily constructed by those ordinarily skilled inthe art. In addition, the normalized detector gain term memory 28 iseasily constructed by those ordinarily skilled in the art and may beimplemented in random access memory (RAM) or electrically ereasableprogrammable read only memory (EEPROM).

Unlike many conventional target detection systems that only account fordetector gain non-uniformities, the present invention accounts for noisenon-uniformities via the application of the correction termsG_(ij)/σ_(ij).

The S_(ij)(G_(ij)/σ_(ij))−B_(ij) terms output from the subtractor 30represent background subtracted video that comprises frames of imagedata. The noise estimator 38 computes noise estimates σ_(ij) ² based onthe background-subtracted video S_(ij)(G_(ij)/σ_(ij))−B_(ij) and inputsthe estimates σ_(ij) ² to the second multiplier 48. The noise estimatesσ_(ij) ² are multiplied with a predetermined threshold multiplier TM_Eprovided via the DSP 52.

The threshold multiplier TM_E may be computed via the use of a fuzzycontroller as discussed more thoroughly below, or via another mechanismwithout departing from the scope of the present invention. The outputTM_E*σ_(ij) ² of the second multiplier 48 represents a threshold levelof the uni-level threshold circuit 40. The threshold multiplier TM_E isset so that when the output TM_E*σ_(ij) ² term is less than the signedsquare of the corresponding background subtracted video termS_(ij)(G_(ij)/σ_(ij))−B_(ij), the ij detector in the sensor 22 is likelyreceiving input electromagnetic energy representative of a target.

The uni-level threshold circuit 40 compares the signed square of thebackground subtracted video S_(ij)(G_(ij)/σ_(ij))−B_(ij), i.e.,(S_(ij)(G_(ij)/σ_(ij))−B_(ij))² with the lower threshold. If the signedsquare of the background subtracted video S_(ij)(G_(ij)/σ_(ij))−B_(ij)exceeds the lower threshold, then the signal output from the ij detectorin the sensor 22 may represent target data or other data that is notdesirable to include in noise estimates. The uni-level threshold circuit40 then outputs an inhibit signal in response thereto to the recursivebackground estimator 32 and the noise estimator 38. The inhibit signaldisables the recursive background estimator 32 and the noise estimator38 thereby preventing target data or spike data output from a givendetector from corrupting the background estimates B_(ij) and the noiseestimates σ_(ij) ², respectively.

By selectively inhibiting the updating of the background estimatesB_(ij) and the noise estimates σ_(ij) ² in response to the reception ofpossible target data by a given detector in the sensor 22, the targetdetection system 20 of the present invention may account for changes insignal environment and detector performance during system operation.This greatly enhances the performance of the target detection system 20.Conventional target detection systems must often refrain from computingbackground estimates and noise estimates during system operation due tothe fact that target data will otherwise corrupt the estimates.

Those skilled in the art will appreciate that the computations performedin the modules such as the noise estimator 38 and the uni-levelthreshold device may be based on averages or accumulations of frames ofimage date without departing from the scope of the present invention.

To further enhance the target detection capability of the targetdetection system 20, the frame integrator 34 and the filter bank 42 areemployed to increase the signal-to-noise ratio (SNR) of the backgroundsubtracted video S_(ij)(G_(ij)/σ_(ij))−B_(ij). The frame integrator 34adds a predetermined number of frames of background subtracted videoS_(ij)(G_(ij)/σ_(ij))−B_(ij), which is three in the present specificembodiment. Signal information in the background subtracted video addscoherently while noise adds non-coherently due to the statisticalcharacteristics of the signal and noise, respectively. As a result, whenframes of the background-subtracted video are summed, the SNR isenhanced. The output of the frame integrator 34 has zero mean.

To account for motion of the target detection system 20 between frames,the background subtracted video S_(ij)(G_(ij)/σ_(ij))−B_(ij) may bere-registered via horizontal or vertical frame shift commands computedby software running on the DSP 52 via input from the inertial referenceunit 58. The shift commands are determined via software easilyconstructed by those ordinarily skilled in the art.

The filter bank 42 is a bank of finite impulse response (FIR) filters(as discussed more fully below). The filter bank 42 filters output fromthe frame integrator 34 and selects the maximum value output from eachof four matched filters. The maximum value is input to the bi-levelthreshold circuit 44 where its signed square is compared to a thresholdrange having an upper threshold and a lower threshold.

The lower threshold is computed via the adder 56 and the thirdmultiplier 50 with inputs from the TNR RAM 54, the noise estimator 35,and the DSP 52. The third multiplier receives TNR values TNR_(ij) fromthe TNR RAM 54 that stores TNR_(ij) values computed by software runningon the DSP 52. The TNRij values compensate for higher order moments,i.e., moments greater than two in the noise statistic σ_(ij). Forexample, if the statistical noise distribution for a given detector inthe sensor 22 is not Gaussian, the TNR_(ij) values may be applied tocompensate for the statistical abnormality. Also, the TNR valuesTNR_(ij) may be used to disable malfunctioning detectors.

The third multiplier 50 also receives a threshold multiplier TM inputfrom the DSP 52. A fuzzy controller, (as discussed more fully below)implemented in software running on the DSP 52, computes the thresholdmultiplier TM based on a desired number of false alarms per frame ofdata received from the sensor 22, and based on the actual number ofalarms detected by the DSP 52 via input from the address generator 46and based on the number of true track detections from a data processor59. Inputs (not shown) to the data processor 59 and the construction ofthe data processor 59 are well known by those ordinarily skilled in theart.

Those skilled in the art will appreciate that another type of controllerother than a fuzzy controller may be used without departing from thescope of the present invention.

The third multiplier 50 multiplies the noise estimates σ_(ij) ² from thenoise estimator 38, TNR values TNR_(ij), and threshold multiplier TM andprovides the resulting output σ_(ij) ²*TNR_(ij)*TM to an input of theadder 56. The adder 56 adds the resulting output σ_(ij) ²*TNR_(ij)*TM toan offset μ_(n), which is a software controllable scale factor thatprovides additional control over the performance of the target detectionsystem 20 and is adjusted according to the requirements of a particularapplication. The offset μ_(n) is global to all detectors in the array.The resulting sum σ_(ij) ²*TNR_(ij)*TM+μ_(n) represents the lowerthreshold value T1 _(ij), which is unique to each detector in the sensor22.

Unlike many existing target detection systems, the present inventionprovides thresholds unique to each detector in the sensor 22 so that thetarget detection system 20 can maximize the use of the performancecapabilities of each individual detector.

The capabilities of higher performing detectors are not compromised dueto unnecessarily high threshold levels applied to the higher performingpixels due to the application of a single threshold based on globaldetector statistics.

The upper threshold T2 of the bi-level threshold circuit 44 is softwarecontrollable and is adjusted in accordance with the performancerequirements for a particular application and is intended to account forgamma spike events and other non-target events that might cause anexceedance of the lower threshold T1 _(ij) by the output of the filterbank 42.

The bi-level threshold circuit 44 compares the signed square of theoutput of the filter bank 42 to the threshold range. If the signedsquare of the output of the filter bank 42 exceeds the lower thresholdT1 _(ij) and is less than the upper threshold T2, a detection or ‘alarm’is indicated for the ij detector via a pulse (such as a 0 or 1) at theoutput of the bi-level threshold circuit 44. The address generator 46receives the output of the bi-level threshold circuit, and provides theaddresses of the detectors associated with the alarms, i.e., providesthe values of i and j to the DSP 52.

The frame store 36 stores the most current background subtracted videovalues S_(ij)(G_(ij)/σ_(ij))−B_(ij). The DSP 52 can use the address ofthe detectors at which alarms have occurred to retrieve associateddetector output values from the frame store 36. The associated detectoroutput values are utilized by target detection software running on theDSP 52. The target detection software may be developed by thoseordinarily skilled in the art.

Various signal delays resulting from computations performed in variouscircuits such as the noise estimator 38, the recursive backgroundestimator 32, and the subtractor 30 are accounted for via theapplication of clocking circuits and delays (not shown) which are easilydesigned and implemented by those ordinarily skilled in the art.

FIG. 2 is a diagram of the recursive background estimator 32 of thetarget detection system 20 of FIG. 1. The. recursive backgroundestimator 32 includes, from left to right, an electrically controllableswitch 70, a background estimator multiplier 72, a background estimatoradder 74, and a background estimate memory 76. The output of the switch70 is connected to an input of the background estimator multiplier 72.Another input of the background estimator multiplier 72 is connected tothe DSP 52 of FIG. 1 via the bus connection 60 and provides a timeconstant to the recursive background estimator 32. The bus connection 60also provides a software read and write connection background estimatememory 76. An output of background estimator multiplier 72 is connectedto an input of the background estimator adder 74. Another input of thebackground estimator adder 74 is connected to an output of thebackground estimate memory 76, which also represents the output of therecursive background estimator 32. The output of the backgroundestimator adder 74 is input to the background estimate memory 76.

The electrically controllable switch 70 switches its output from thebackground subtracted video S_(ij)(G_(ij)/σ_(ij))−B_(ij) to a groundconnection in response to an inhibit signal from the uni-level thresholdcircuit 40 of FIG. 1. Those skilled in the art will appreciate that theelectrically controllable switch 70 may be implemented as a 2 to 1multiplexer. The inhibit signal thereby deactivates the recursivebackground estimator 32 when the uni-level threshold circuit of FIG. 1detects an exceedance of the corresponding lower threshold T1_E_(ij).

The DSP 52 has software read and write access to the background estimatememory 76, which is implemented in RAM in the present specificembodiment. The background estimate memory 76 is be implemented viaanother type of memory such as an electrically erasable programmableread only memory (EEPROM) without departing from the scope of thepresent invention.

The recursive background estimator 32 provides temporally adaptive meanbackground estimation localized to each detector of the sensor 22 ofFIG. 1. The recursive background estimator 32 is implemented as adigital single pole infinite impulse response (IIR) filter having afilter time constant under software control that is changeable at theframe rate of the sensor 22 of FIG. 1.

The recursive background estimator 32 may update continuously, or beinhibited from updating as a result of an inhibit signal provided viathe uni-level threshold circuit or via a global software inhibit signal.The global inhibit signal applies to all detectors in the sensor 22 ofFIG. 1 and is selectively provided at an input of the backgroundestimator multiplier 72.

With reference to FIGS. 1 and 2, when not globally inhibited fromupdating, a feedback signal, unique to each detector in the sensor 22,from the uni-level threshold circuit 40, inhibits background updates ondetectors that have a threshold exceedance, or are neighbors ofdetectors which have a threshold exceedance. This feature preventstarget data from corrupting the background estimates.

FIG. 3 is a diagram of the noise estimator 38 of the target detectionsystem 20 of FIG. 1. The noise estimator 38 includes, from left toright, an inhibit switch 80 a first noise estimator multiplier 82, anoise estimator subtractor 84, a second noise estimator multiplier 86, anoise estimator adder 88, and a noise variance memory 90.

The operation of the inhibit switch 80 is similar to the operation ofthe electrically controllable switch 70 of FIG. 2. The output of theinhibit switch 80 is squared via the first noise estimator multiplier 82and output to a positive terminal of the noise estimator subtractor 84,the negative terminal of which is connected to an output of the noisevariance memory 90, which is similar to the background estimate memory76 of FIG. 2. An output of the noise estimator subtractor 84 isconnected to an input of the second noise estimator multiplier 86, asecond input of which is connected to the bus connection 60, whichprovides a time constant to the multiplier 86 via the bus connection 60and the DSP 52.

With reference to FIGS. 1 and 3, a signal from the DSP 52 may be used toglobally inhibit noise estimates from being performed on all detectorsin the sensor 22. An inhibit signal from the uni-level threshold circuit40 is input to the inhibit switch 80 and selectively inhibits noiseestimates from being computed by the noise estimator 38 for theparticular detectors having outputs associated with an exceedance of thethreshold of the uni-level threshold circuit 40.

The noise estimator 38 provides noise variance estimation localized toeach detector in the sensor 22. The gain-normalized andbackground-subtracted video S_(ij)(G_(ij)/σ_(ij))−B_(ij) is squared andfiltered to develop an estimate of the detector noise variance. Thenoise estimator 38 is a single pole IIR filter with the filter timeconstant under software control and changeable at the frame rate of thesensor. The noise estimator 38 can be allowed to update continuously atthe sensor frame rate, or can be inhibited from updating as a result ofa global inhibit signal generated by software and applied via the busconnection 60 and the second noise estimator multiplier 86. In thepresent specific embodiment, the noise variance memory 90 is a softwareread/write RAM and provides read/write access to software functionsrunning on the DSP 52 of FIG. 1 via the bus connection 60. With accessto noise variance terms stored in the noise variance memory 90, softwarefunctions can compensate the outputs of individual detectors in thesensor 22 for noise on-uniformity. This compensation is accomplished bydividing the gain correction factor by G_(ij) by the square root of thenoise variance estimate output from the noise variance memory 90. Thegain correction factors divided by the square roots of the noiseestimates are stored in the normalized detector gain term memory 28 ofFIG. 1.

FIG. 4 is a diagram of the frame integrator 34 of the target detectionsystem 20 of FIG. 1. An input of the frame integrator 34 is provided toan input of a frame integrator multiplexer (MUX) 100. The MUX 100provides output, in parallel, to a first frame store 102, a second framestore 104, a third frame store 106, and a fourth frame store 108, andstores consecutive frames in adjacent frame stores. The most recentframe of data received by the MUX 100 is stored in the first frame store102 and the second most recent frame of data is stored in the secondframe store 104 and so on. Outputs of the frame stores 102, 104, 106,and 108 are input to a frame summing circuit 110 that selects the threemost recent frames of data and adds them. Before summing, the framesumming circuit 40 applies any frame shifts required to spatiallyregister the frames to the nearest pixel, in response to movement of thetarget detection system 20. In the present discussion, pixels correspondto background subtracted and gain corrected outputs of individualdetectors in the sensor 22 of FIG. 1.

With reference to FIGS. 1 and 4, any necessary frame shift signals areprovided by the software running on the DSP 52 that takes into accountsystem movement via use of the IRU 58.

The MUX 100, the frame stores 102, 104, 106, and 108, and the framesumming circuit 100 may be easily constructed by those ordinarilyskilled in the art. In addition, the frame integrator 34 may be replacedwith a different frame integrator, such as one implemented in software,without departing from the scope of the present invention.

The frame integrator may be selectively bypassed via a bypassingmultiplexer (not shown) and a control signal input from the DSP 52 ofFIG. 1 to the bypassing multiplexer. The frame integrator 34 may beselectively bypassed in other ways without departing from the scope ofthe present invention.

FIG. 5 is a diagram of the matched filter bank 42 of the targetdetection system 20 of FIG. 1. A matched filter bank MUX 120 receives aninput of the filter bank 42 corresponding to an output of the frameintegrator 34 of FIG. 1. The MUX 42 has four outputs, each of which isconnected to one of four matched finite impulse response (FIR) filters122. A frame of image data is input to different matched filters 122 viathe MUX 120. The outputs of the matched filters 122 are connected to amaximization circuit 124 that selects the matched filter output signalhaving the largest value. The maximum filtered value output to thebi-level threshold circuit for threshold comparisons.

FIG. 6 is a diagram of a diagram of a finite impulse response (FIR)filter 122 of the filter bank 42 of FIG. 5. The FIR filter 122 is 3×3spatial FIR filter whose transfer function if convolved with frame data.The transfer functions, represented by the coefficients f_(ij), areconvolved with frame data and are designed to boost target SNR.Typically, the filter coefficients f_(ij) are matched to a convolvedoptical point spread function (OPSF) of the sensor 22 of FIG. 1 for upto four different phasings of the OPSF on the ij detector of the sensor22. The coefficients f_(ij) are normalized to preserve total noise powerof the zero-mean input signal from the frame integrator 34 of FIG. 1.

Those skilled in the art will appreciate that a filter kernel other thana 3×3 filter kernel, such as a 5×5 or 7×7 filter kernel may be used forthe FIR filter 122 without departing from the scope of the presentinvention.

With reference to FIGS. 1 and 6, the DSP 52 has software read/writeaccess to the coefficients f_(ij) and can change the coefficients f_(ij)at the frame rate of the sensor 22. This facilitates matching of thefilter coefficients f_(ij) to the velocity of a point source targetacross the detector array of the sensor 22 via inputs from the IRU 58.

FIG. 7 is a diagram showing key functional blocks of a fuzzy thresholdcontroller implemented in the digital signal processor 52 of the targetdetection system 20 of FIG. 1. The fuzzy threshold controller 130includes a target detection counter 132, an input of which is connectedto the address generator 46 of FIG. 1. An output of the target detectioncounter 132 is connected to one input of a fuzzifier input calculationcircuit 134, another input of which is connected to a first output of aninput device 136. Second and third outputs of the input device 136 areconnected to a threshold multiplier initializer 138. An output of thefuzzifier input calculation circuit 134 is input to a fuzzifier 140, theoutput of which is connected, in parallel to an inference engine 142 andto an input of a defiler 144. An output of the inference engine 142 isconnected to another input of the defuzzifier 144, the output of whichis connected to an input of a fuzzy threshold controller multiplier 146.Another input of the fuzzy threshold controller multiplier 146 isconnected to an output of a ΔTM calculator 148, the input of which isconnected to the first output of the input device 136. The first outputis also connected to an input of the fuzzifier input calculation circuit134. An output of the fuzzy threshold controller multiplier 146 isconnected to an input of a fuzzy threshold controller adder 150, anotherinput of which is connected to a frame delay circuit 152. An input ofthe frame delay circuit 152 is connected to an output of the fuzzythreshold controller adder 150 and another input of the frame delaycircuit 152 is connected to an output of the TM initializer 138.

In operation, the target detection counter 132 receives an input fromthe address generator 46 of FIG. 1 and outputs the number of alarms,i.e., the number of detections (N) received in an image frame to afuzzifier input calculation circuit 134. The desired number of falsedetections may be adjusted in accordance with the performancerequirements for a particular application. Those skilled in the art willappreciate that the target detection counter 132 may be designed toreceive input directly from the bi-level threshold circuit 44 withoutdeparting from the scope of the present invention.

The input device 136, which may be implemented as a keypad, allows auser to input a desired number of detections ({overscore (N)}) to bereceived by the target detection counter 132 during a frame.

The fuzzifier input calculation circuit provides an input to thefuzzifier 140 that is computed in accordance with the followingequation:

(N−{overscore (N)})/({overscore (N)})^(½),   [1]

where N is the number of detections in a frame and {overscore (N)} isthe desired number of detections in a frame.

The fuzzer 140 computes a fit vector I={a1, a2. . . , am} in accordancewith an input feature (as discussed more fully below). In the presentspecific embodiment, m is 7, which corresponds to the number of inputregions of the input feature. Each (N−{overscore (N)})/({overscore(N)})^(½) value is mapped into a predetermined number of input regions,i.e., sets Ai, and each value is assigned a particular degree of fit inthe associated input regions in accordance with the rules of the inputfeature. In the present specific embodiment, i ranges from 1 to 7 and isthe number of input regions of the input feature. For example, aparticular value for (N−{overscore (N)})/({overscore (N)})^(½) may causethe fuzzifier to activate first and second input regions of the inputfeature, and assign the input (N−{overscore (N)})/({overscore (N)})^(½)degrees of fit a1 and a2 corresponding to the first and second regions,respectively. This results in a fit vector of I={a1, a2, 0, 0, 0, 0, 0}.

The fuzzifier 140 maps continuous measurements ((N−{overscore(N)})/({overscore (N)})^(½)) into membership values in the input fuzzysets Ai. Let the input measurement be the variable x=(N−{overscore(N)})/({overscore (N)})^(½), and let the domain of x be the interval[x_(a), x_(b)]. The input space is spanned by the set {Ai} of inputfuzzy sets Ai for i=1, 2, . . . , m, where m is 7 in the presentspecific embodiment. A membership function μ_(i)(x) is associated witheach fuzzy set Ai. The membership function μ_(i)(x) maps, via thefuzzifier 140, the input x into the degree of membership in Ai resultingin the input fuzzy vector I={a1, a2, . . . , am} where ai is themembership value of the input x in the ith fuzzy set Ai and can take onvalues in the interval [0,1] in the present specific embodiment.

The fit vector I is input to the inference engine 142. The inferenceengine 142 maps elements of the fit vector I into output regions, i.e.,sets Bj having centroids Cj and areas Rj, in accordance with rules of anoutput feature (as discussed more fully below). In the present specificembodiment, j ranges from 1 to 7, where 7 is the number of outputregions of the output feature.

The inference engine 142 maps the input fuzzy sets Ai into the outputfuzzy sets Bj in accordance with the rules of the output feature. In thepresent specific embodiment, the rules of the output feature are of theform if (A) then (B). The fuzzy threshold controller utilizes seveninput fuzzy sets Ai and seven output fuzzy sets Bj, each set Ai and Bjhaving elements given the linguistic names LN, MN, SN, ZERO, SP, MP, LPwhich stand for large negative, medium negative, small negative, zero,small positive, medium positive, and large positive, respectively. Thefollowing table defines seven fuzzy rules implemented by the inferenceengine 142.

TABLE 1 (Ai; Bj(i)) (LN; LP) (MN; MP) (SN; SP) (ZERO; ZERO) (SP; SN)(MP; MN) (LP; LN)

The output fuzzy set Bj(i) is the jth output fuzzy set and is associatedwith the ith input fuzzy set Ai. The fuzzy rules are of the form(Ai;Bj(i)), which is interpreted as “If the input fuzzy set is Ai, thenthe output fuzzy set Bj(i) is activated”. For example, if the inputfuzzy set LP is activated, the inference engine 142 activates the outputfuzzy set LN.

The defuzzifier 144 computes an output ({overscore (y)}) based on alinear combination of elements ai of the input fit vector I and thecorresponding output regions having centroids Cj(i) and areas Rj(i). Theoutput of the defuzzifier 144 is a weighted centroid computed inaccordance with the following equation: $\begin{matrix}{{\overset{\_}{y} = {\sum\limits_{i = 1}^{m}{{ai}*{{Rj}(i)}*{{{Cj}(i)}/{\sum\limits_{i = 1}^{m}{{Rj}(i)}}}}}},} & \lbrack 2\rbrack\end{matrix}$

The output {overscore (y)} of the defuzzifier 144 is multiplied with adelta threshold multiplier (ATM) via the multiplier 146. ΔTM is computedin accordance with the following equation:

ΔTM=−2/{square root over ({overscore (N)})},  [3]

where {overscore (N)} is the desired number of alarms in an image frame.The output of the multiplier 146 is {overscore (y)}*ΔTM and is added tothe output of the frame delay 152 via the adder 150. The output of theframe delay is either an initial threshold multiplier value provided bythe TM initializer 138 or the output of the adder 150 delayed by oneframe. The TM initializer is selectively activated via an enableconnection from the input device 136. The TM initialzier may beactivated by user input via the input device 136 or may be activated byanother means without departing from the scope of the present invention.

The TM initializer 138 computes the initial value TM in accordance withthe following equation:

TM=2*(erf¹(1−2*Pfa))²,  [4]

where Pfa is the desired probability of false alarms and is specified bya user via the input device 136. The output of the fuzzy thresholdcontroller adder 150 represents the global threshold multiplier TM andis input to the third multiplier 50 of FIG. 1.

With reference to FIGS. 1 and 7, the global threshold multiplier TMcontrols the values of the thresholds T1 _(ij) for detectors in thedetector array of the sensor 22 in the bi-level threshold circuit 44.The fuzzy threshold controller 130 may be implemented in software orhardware by those ordinarily skilled in the art. The fuzzy thresholdcontroller 130 maintains a constant threshold exceedance rate, i.e., aconstant probability of false alarm (Pfa) which may be specified by auser via the input device 136. The fuzzy threshold controller 130monitors the number of alarms during a predetermined time interval andadjusts the threshold multiplier TM and thereby the lower threshold T1_(ij) accordingly.

The input device 136 includes a memory device (not shown) that maintainsa nominal value {overscore (N)} for the desired number of detections perframe. The actual number of false detections N associated with a givenframe is compared to the nominal value {overscore (N)}. The fuzzythreshold controller 130 incrementally changes the TM by an amount ΔTNRbased on the normalized deviation between the actual number of noisydetections N and the nominal value {overscore (N)}, i.e., (N−{overscore(N)})/({overscore (N)})^(½).

Additional fuzzy logic controllers (not shown) identical to the fuzzylogic controller 130 may be implemented to control the false alarm ratedue to the presence of periodic noise spikes in the sensor frame data.

FIG. 8 is a graph of the input feature 160 of the fuzzy thresholdcontroller 130 of FIG. 7. The input feature 160 includes seven sets Aicorresponding to the regions labeled MN, SN, ZERO, SP, MP and LP. Ahorizontal axis 162 represents the input x=(N−{overscore(N)})/({overscore (N)})^(½). A vertical axis 164 represents degrees offit. For example, if the input is approximately 5, the MP region and theLP regions are activated. The MP region is activated with a degree offit of approximately {fraction (1/2)} and the LP region is activatedwith a degree of fit of 1. The fit vector I={a1, . . . am} will containthe elements {fraction (1/2)} and 1. The corresponding output fuzzy setsBj(i), i.e., the sets MN and LN of the output feature will be activatedin accordance with the fuzzy rules depicted in Table 1 and as discussedmore fully below.

FIG. 9 is a graph of the output feature 170 of the fuzzy thresholdcontroller 130 of FIG. 7. The output feature 170 includes seven setsBj(i) corresponding to the regions labeled LN, MN, SN, ZERO, SP, MP, andLP. An output feature horizontal axis 172 represents y values internalto the inference engine 142. An output feature vertical axis 174represents a degree of membership in each of the output regions LN, MN,SN, ZERO, SP, MP, and LP.

With reference to FIGS. 7, 8, and 9 if (N−{overscore (N)})/({overscore(N)})^(½) is large, for example 8, the number of detections N is muchlarger than the desired number of detections N. The LP region of theinput feature 160 is activated. The inference engine 142 then activatesthe LN output region. With reference to equation (2), because absolutevalues of the centroid Cj(i) and corresponding area Rj(i) of the LNoutput region are relatively large, the output {overscore (y)} of thedefuzzifier 144 will be a relatively large negative value due to thenegative centroid value Cj(i). The output of the multiplier 146 will bea relatively large positive value after multiplication by ΔTM, which isnegative. When the output of the multiplier 146 is added to the previousTM via the adder 150, the output of the adder 150 will yield anappropriate increase in the TM. The resulting higher threshold levelwill result in a reduction of the number of detections N and hence,(N−{overscore (N)})/({overscore (N)})^(½) will be become smaller. Inthis way, the fuzzy controller 130 of FIG. 7 facilitates the maintenanceof an approximately constant probability of false alarms in a particularframe in accordance with the desired number of alarms {overscore (N)}.

Thus, the present invention has been described herein with reference toa particular embodiment for a particular application. Those havingordinary skill in the art and access to the present teachings willrecognize additional modifications, applications and embodiments withinthe scope thereof.

It is therefore intended by the appended claims to cover any and allsuch applications, modifications and embodiments within the scope of thepresent invention. Accordingly,

What is claimed is:
 1. An accurate target detection system comprising:first means for receiving electromagnetic signals and providingelectrical signals in response thereto, said first means including anarray of electromagnetic energy detectors, each detector providing anelectrical detector output signal; second means for correctingnon-uniformities in said first means based on said electrical signalsand providing calibrated electrical signals in response thereto, saidsecond means including means for compensating for gain, background, andnoise non-uniformities in said electromagnetic energy detectors and adetector gain term memory for storing detector gain compensation values,said detector gain compensation values normalized by noise estimates;third means for determining if a target signal is present within saidcalibrated electrical signals and providing a target detection signal inresponse thereto; and fourth means for selectively activating ordeactivating said second means based on said target detection signal. 2.The invention of claim 1 wherein said noise estimates are unique to eachof said detectors.
 3. The invention of claim 1 wherein said third meansincludes means for increasing the signal-to-noise ratio of saidcalibrated electrical signals.
 4. The invention of claim 3 wherein saidthird means includes means for estimating noise in each of said detectoroutput signals and providing noise estimates in response thereto.
 5. Theinvention of claim 4 wherein said means for estimating noise furtherincludes means for recursively estimating background in said electricalsignals.
 6. The invention of claim 5 wherein said means for estimatingnoise includes a noise estimator circuit and a recursive backgroundestimator circuit.
 7. The invention of claim 4 wherein said third meansfurther includes a subtractor for subtracting background from saidcalibrated electrical signals and providing background subtractedsignals in response thereto.
 8. The invention of claim 7 wherein saidmeans for increasing the signal-to-noise ratio of said electricalsignals includes means for adding frames of image data, each framecontaining data corresponding to said background subtracted signals andproviding summed frames in response thereto.
 9. The invention of claim 8wherein said means for increasing the signal-to-noise ratio furtherincludes a filter bank for increasing the signal-to-noise ratio of saidsummed frames and providing a filtered signal in response thereto. 10.The invention of claim 9 wherein said filter bank includesfinite-impulse response filters.
 11. The invention of claim 9 whereinsaid third means includes a first threshold circuit for comparing saidfiltered signal to a first threshold and a second threshold andproviding a threshold exceedance signal if said filtered signal isbetween said first threshold and said second threshold.
 12. Theinvention of claim 11 wherein said third means further includes adigital signal processor running a fuzzy controller that facilitates thedetermination of said first threshold by providing a thresholdmultiplier value.
 13. The invention of claim 12 wherein said firstthreshold is a function of said threshold multiplier and noise variablesfor said background subtracted signals.
 14. The invention of claim 13wherein said noise variables include a mean noise offset, noise varianceestimates from said background subtracted signals, and a noise statisticfor accounting for moments greater than two in noise statistics of saidbackground subtracted signals.
 15. The invention of claim 7 wherein saidfourth means includes a second threshold circuit for comparing saidbackground subtracted signals to a target detection threshold andproviding said target detection signal in response thereto when saidbackground subtracted signals exceed said target detection threshold.16. The invention of claim 15 wherein said target detection signal actsas an inhibit signal and is input to said means for estimating noise todisable said means for estimating noise when said target signal ispossibly present with in said background subtracted signals.
 17. Theinvention of claim 15 wherein said first threshold is a function of saidnoise variance estimates, and a second threshold multiplier.
 18. Anaccurate target detection system comprising: fisrt means for receivingelectromagnetic signals and providing electrical signals in responsethereto, said first means including an array of electromagnetic energydetectors, each detector providing an electrical detector output signal;second means for correcting non-uniformities in said first means basedon said electrical signals and providing calibrated electrical signalsin response thereto; third means for determining if a target signal ispresent within said calibrated electrical signals and providing a targetdetection signal in response thereto, said third means including meansfor increasing the signal-to-noise ratio of said calibrated electricalsignals and means for estimating noise in each of said detector outputsignals and providing noise estimates in response thereto; and fourthmeans for selectively activating or deactivating said second means basedon said target detection signal.
 19. An accurate target detection systemcomprising: first means for receiving electromagnetic signals andproviding electrical signals in response thereto, said first meansincluding an array of electromagnetic energy detectors, each detectorproviding an electrical detector output signal; second means forcorrecting non-uniformities in said first means based on said electricalsignals and providing calibrated electrical signals in response thereto;third means for determining if a target signal is present within saidcalibrated electrical signals and providing a target detection signal inresponse thereto, said third means including means for estimating noisein each of said detector output signals and providing noise estimates inresponse thereto; and fourth means for selectively activating ordeactivating said second means based on said target detection signal.